发明名称 CLOCK PHASE PULLING IN AND FOLLOWING DEVICE AND PHASE PULLING IN METHOD
摘要 PROBLEM TO BE SOLVED: To shorten a time required for pulling in a phase. SOLUTION: This device 1 is provided with a phase error calculating part 2 calculating a phase error with respect to a prescribed quantization timing of the signal subjected to a quantization and clock generating part 3 generating a clock at a prescribed clock based on the phase error information calculated in the phase error calculating part 3 and also is made so as to perform a judgement in which a threshold value set based on the signal quantized in the past is used as to the signal subjected to the quantization at the time of calculating the phase error in the phase error calculating part 2 when the pulling-in the clock phase is started.
申请公布号 JPH10241301(A) 申请公布日期 1998.09.11
申请号 JP19970042760 申请日期 1997.02.26
申请人 FUJITSU LTD 发明人 SUGAWARA TAKAO
分类号 G11B20/14;H03L7/00;H03L7/081;H03L7/091;H04L7/02 主分类号 G11B20/14
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