| 摘要 |
PROBLEM TO BE SOLVED: To obtain a stable, high-speed CMOS circuit with small power consumption by controlling the well voltage of the CMOS circuit at the time of a power-ON operation, a normal operation, and a power-OFF operation. SOLUTION: When the power source is turned ON, a circuit block CT 2 selects voltages which are high enough to cut off transistors, i.e., 3.3V for a PMOS FET and -1.5V for an NMOSFET. Then a low voltage VCC2 is applied. The threshold voltage VT of the transistor is sufficiently high, so subthreshold currents are not accumulated to generate an excessive chip current, so no latch-up phenomenon is caused. In the normal operation, the voltage of substrates NW and PW are made shallow (2.3V and -0.5V) and the threshold voltage VT is made low for the operation, thereby reducing the power consumption. When the power source is turned OFF, the substrate voltages are made sufficiently high, the VCC2 is turned OFF, and then the source voltage VCC1 is turned OFF. When the source voltages are applied, the high source voltage VCC1 is applied and then the low source voltage VCC2 is inputted. |
