| 摘要 |
<p>PROBLEM TO BE SOLVED: To permit the internal circuit characteristics to be easily tested without increasing the chip size of a multilayer structured semiconductor device. SOLUTION: The multilayer-wired semiconductor device 1 comprises electrodes (pads) formed on the entire wiring pattern surface thereof with probe wiring terminals 3 at lower layers thereof. When probing, the metal of the electrodes 2 is locally removed to expose the wiring terminals 3, using a machining technology, and a probing technology such as electron beam 7 is applied to the exposed terminals 3 to check the circuit characteristics, thereby clarifying the characteristics of a circuit built into the lower layer or the working condition of a specific wiring.</p> |
