| 摘要 |
PROBLEM TO BE SOLVED: To achieve the high speed, the large capacity and the large scale of a synchronous SRAM or the like and the high speed and the high performance of an engineering workstation(EWS) or the like containing the SRAM or the like as a cache memory. SOLUTION: In a synchronous SRAM or the like which constitutes a cache memory for an EWS, e.g. a noninverting data line Wtn and an inverting data line Wbn in a complementary data line Wn* which constitutes a memory array are formed by using, e.g. a second-layer metal wiring layer M2 and a third-layer metal wiring layer M3 whose formation height is different. Thereby, the line-to-line capacitance of a noninverting signal line and that of an inverting signal line in every complementary data line are reduced, and the level of every data line is changed at high speed. Inversely, while an increase in line-to-line capacitance is being suppressed, the wiring pitch between the complementary data lines is reduced, and the high integration of the memory array is achieved. |
