| 摘要 |
<p>PROBLEM TO BE SOLVED: To eliminate an error in the case of setting a delay in a variable delay circuit. SOLUTION: An NMOS 12 provides resistance in response to a control signal S30 and configures a delay means tog ether with a capacitor 13. An input pulse signal Sin is delayed by a buffer 11, an NMOS 12 and the capacitor 13 and the delayed signal is given to a buffer 14, from which an output pulse signal Sout is outputted. A phase difference between the signal Sout and the signal Sin is extracted by an exclusive OR circuit 21, and a mean value detection circuit 22 obtains a mean value of phase differences. A comparator 31 compares the mean value obtained by the mean value detection circuit 22 with an output level Vt1 of a variable reference power supply 32 and gives a control signal S30 to a gate of the NMOS 12 for automatically control so that they are coincident with each other and the delay in the signal Sout is made constant. Thus, a desired delay amount is obtained by monitoring the mean value outputted from the mean value detection circuit 22 so as to adjust the output level Vt1.</p> |
