| 摘要 |
<p>A dynamic RAM having two-transistor memory cells includes a top array of memory cells and a bottom array of memory cells, with a sense amplifier disposed between the two halves. The memory cells in each column of the top half are coupled to respective Bit_Plus lines, and the memory cells in each column of the bottom half are coupled to respective Bit_Minus lines. The Bit_Plus lines and the Bit_Minus lines are respectively coupled to Plus and Minus inputs of sense amplifiers for each column. One row of the top array includes only dummy cells, and one row of the bottom array includes only dummy cells. When a memory cell in the top array is read, a dummy cell in the lower array is activated, and when a memory cell in the bottom array is read, a dummy cell in the upper array is activated. That way, a two-transistor memory cell array can have a dual-differential bit line feature in order to reduce errors due to noise.</p> |
