SRAM P-CHANNEL MOS TRANSISTOR SELF-ALIGNED OFFSET STRUCTURE

摘要

PROBLEM TO BE SOLVED: To provide an SRAM p-channel MOS transistor self-aligned offset structure which reduces the leakage current of pMOS transistor memory cells. SOLUTION: A p-channel MOS transistor has a gate electrode 30, a source electrode 31 and a drain electrode 32 formed on a semiconductor substrate and is used as a load of an SRAM cell. A high-resistance offset 28 is provided between the drain and the source electrodes 32, 31 and directly formed on the gate electrode 30 between these electrodes 32, 31 during a process of a photo mask for the gate electrode 30, without using an extra manufacturing step and photo mask.