Dynamic logic circuit and self-timed pipelined datapath system

摘要

A dynamic logic circuit comprising a plurality of unit dynamic logic circuits (21, 23, 31, 33) sequentially coupled in a multiple-stage fashion, each of which unit dynamic logic circuits including: a logic circuit portion (21, 31) formed by one or more than one MOS transistors (MN21, MN22, MP32, MP33); a first MOS transistor for a precharging (MP21) or a pre-discharging (MN31) operation with respect to the logic circuit (21, 31); and a second MOS transistor to enable the logic circuit a discharging (MN23) or a charging (MP31) operation; wherein the MOS transistors (MN21, MN22, MP32, MP33) composing the logic circuit portion (21, 31) are configured by low-threshold MOS transistors; and the second MOS transistor to enable the discharging (MN23) or charging (MP31) operation is composed of a high-threshold MOS transistor. The dynamic circuit is applied to a plural stage of combinational circuits (11A, 12A) in a self-timed pipelined datapath system, whereby a static leakage current at charging or pre-discharging operation can be reduced, resulting in decrease of power dissipation. <IMAGE>