发明名称 ATM node and routing data registering apparatus
摘要 A CPU sets one of first and second memories as an "active system memory" and the other as a "standby system memory". Data about a combination of the VPI/VCI and TAG data is registered in and deleted from only the memory set as the "active system memory". The CPU, only when a null entry exists in a position satisfying a VPI/VCI increasing sequence with an increased address value, registers this null entry in the active system memory with data about new combination of the VPI/VCI and the TAG data. Whereas if there is no such null entry, the CPU reads the data about all the combinations of the VPI/VCI and the TAG data which are registered in the active system memory, re-sorts the read data and the data about the new combinations in the VPI/VCI increasing sequence and write the data from the head address in the standby system memory in a sorting sequence. The CPU, when finishing this writing process, resets the memory so far working as the standby system to an active system memory and the memory so far working as the active system to a standby system memory.
申请公布号 US5805592(A) 申请公布日期 1998.09.08
申请号 US19960624941 申请日期 1996.03.22
申请人 FUJITSU LIMITED 发明人 HATANO, TAKASHI
分类号 H04Q3/00;H04L12/56;H04Q11/04;(IPC1-7):H04L12/56 主分类号 H04Q3/00
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