| 摘要 |
<p>PROBLEM TO BE SOLVED: To greatly increase the speed of a reading operation in a stable manner by eliminating the necessity of forcible bit line initialization for each reading cycle. SOLUTION: When the potential Vb of a bit line is higher than that of a reference voltage Vbref by precharging, the output of the comparator C1 of a comparison circuit 12 is inverted from a low signal to a high signal, outputted to the bit line potential initialization control unit 13 of a rear stage and synchronized with a clock signalϕby this bit line potential initialization control unit 13 to produce a wait signal WAIT, and ROM makes a wait request to CPU. Then, during a reading operation, an initialization signalϕDis is outputted from the bit line potential initialization control unit 3 to make a switching element 11 conductive and then the potential Vb of a bit line is initialized to a ground potential.</p> |
