发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain the phase locked loop PLL circuit of which a reference leakage is reduced and a lockup time speed is increased. SOLUTION: In the PLL circuit where a charge pump current is selected, a pulse width generator 27 identifies a difference of pulse width between an up-pulse signal S22a and a down-pulse signal 22b to control an output current of a charge pump circuit 23, and in the case that the PLL circuit is not locked and the pulse width is large, an output current of the charge pump circuit 23 is increased to quicken change in charges given to a loop filter 24. In the case that the PLL circuit is locked and the difference of the pulse width is small, the output current of the charge pump circuit 23 is decreased. Thus, the lockup time of the PLL circuit is decreased and the effect of an external disturbance on the loop filter is reduced and a reference leakage is reduced.
申请公布号 JPH10233681(A) 申请公布日期 1998.09.02
申请号 JP19970034661 申请日期 1997.02.19
申请人 SONY CORP 发明人 MATSUMOTO ISAO
分类号 H03L7/093;H03L7/107 主分类号 H03L7/093
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