| 摘要 |
An instruction translation look-aside buffer (iTLB) for attaining very high data processing throughput comprises a 2n-way set associative data array having m sets, where m and n are both integers greater than or equal to one, with associated data and tag arrays. A set address selects one of the m sets for reading, resulting in a readout of all 2n ways of the tag, valid and data arrays. Comparison logic determines if a match exists between the 2n tags read out from the tag array with a portion of the linear address. A "hit" to a certain way causes a hit line signal to select data for the corresponding way, which is output from a 2n:1 static multiplexer and contains the physical address translation. Each of the hit lines are precharged during a first phase of a clock cycle. The comparison logic operating during a second phase of a clock cycle. Thus, the matching is accomplished in a single clock cycle.
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