发明名称 |
Method and apparatus for increasing processor performance |
摘要 |
A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a cache register file, indexed via the offset field of the load instruction, for retaining cache lines from previously executed load instructions. The cache register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.
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申请公布号 |
US5802564(A) |
申请公布日期 |
1998.09.01 |
申请号 |
US19960676785 |
申请日期 |
1996.07.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORP. |
发明人 |
EICKEMEYER, RICHARD JAMES;MALIK, NADEEM;SAHA, AVIJIT;WARD, CHARLES GORHAM |
分类号 |
G06F9/30;G06F9/38;G06F12/08;(IPC1-7):G06F9/30;G06F12/02;G06F13/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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