| 摘要 |
In a cache memory device including a DRAM cell array, a DRAM cell circuit is connected to word lines. A sense amplifier and a write amplifier are provided to the DRAM cell circuit for writing a certain data signal into one of memory cells connected to a selected word line. A read amplifier as well as the sense amplifier is provided to read data from one of the memory cells to generate a validity signal for showing whether data of the DRAM cell array is valid or invalid.
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