发明名称 |
Error detector for error detecting codes |
摘要 |
There is disclosed an acceptable error detector for error correcting block codes, in which of received syndrome vectors S for the received word vectors Y available from the syndrome generator, the me-bit received subsyndromes S(me) formed by the same components as those of the me-bit representative subsyndromes <S(me)> uniquely corresponding to the vectors of all the acceptable error pattern with error bits equal to or less than the acceptable number e is applied as addresses into the redundant subsyndrome table memory. Since the stored data specified by the input address are (m-me)-bit redundant subsyndromes <S(m-me)> which are supposed to appear in the remaining portion of S(=<S>) when the number of error bits is equal to or less than e, the remaining (m-me)-bit received subsyndromes S(m-me) derived from the received word vector Y in the syndrome generator and the (m-me)-bit redundant subsyndrome <S(m-me)> obtained from the redundant subsyndrome table memory are compared with each other by a coincidence detector to detect coincidence or noncoincidence therebetween. By this configuration, it is possible to detect whether the number of error bits in received word is acceptable.
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申请公布号 |
US5802078(A) |
申请公布日期 |
1998.09.01 |
申请号 |
US19960736260 |
申请日期 |
1996.10.24 |
申请人 |
KOKUSAI ELECTRIC CO., LTD. |
发明人 |
URABE, KENZO;MAKINO, GIHO;TOCHIHARA, SYUNJI;MURAYAMA, YASUHIRO;HOSHI, ATSUSHI |
分类号 |
H03M13/15;(IPC1-7):G06F11/00 |
主分类号 |
H03M13/15 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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