DATA PROCESSING SYSTEM

摘要

A data processing system is provided with a microprocessor (4) with an ECL circuit incorporated in its arithmetic section and a CMOS peripheral circuit (5) which is accessed by the microprocessor (4) through a bus (2). The circuit (5) is provided with a first amplitude converting circuit (51) which outputs the CMOS signal of an internal circuit to the bus (2) after converting the amplitude of the signal to an intermediate amplitude which is smaller than that of the CMOS signal and larger than that of an ECL signal and captures signals which have the intermediate amplitude and are supplied from the bus (2) after converting the amplitude of the signals into that of the CMOS signal. The microprocessor (4) is provided with a second amplitude converting circuit (41) which outputs signals having the amplitude of the ECL signal from an internal circuit to the bus (2) after converting the amplitude of the signal into the intermediate amplitude and captures signals which have the intermediate amplitude and are supplied from the bus (2) after converting the amplitude of the signals into that of the ECL signal. The amplitude converting operations of the circuits (51 and 41) become shorter as compared with such a case that the ECL and CMOS signal levels are directly converted and the signals transmitted to the bus (2) become higher in noise resistance. Therefore, the high-speed data processing ability of the microprocessor with the ECL circuit incorporated in its arithmetic section can be supported by increasing the signal transmitting speed on the bus (2) and, in addition, the increase of the noise reducing cost and peripheral LSI procuring cost can be suppressed.