发明名称 INTEGRATED CIRCUIT FLOOR PLAN OPTIMIZATION SYSTEM
摘要 A method for planning floor allocation of an integrated circuit to each function is disclosed. To provide enough core space to each of the functions and to meet some cost functions such as space utilization requirement of each of the functions, the disclosed method divides the core space to a grid of elementary regions. Then, pieces of the core space are defined and the pieces containing the borders and the overlapping areas of the functions are identified. Then, the identified pieces are used to shift the allocated capacities of the functions as to shift excess capacity or core space from the functions with excess capacity to the functions with a shortage of capacity.
申请公布号 WO9837573(A2) 申请公布日期 1998.08.27
申请号 WO1998US02542 申请日期 1998.02.10
申请人 LSI LOGIC CORPORATION 发明人 SCEPANOVIC, RANKO;ANDREEV, ALEXANDER E.;PASIVIC, IVAN
分类号 G06F17/50 主分类号 G06F17/50
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