Kapazitiver Mikrosensor mit geringer parasitärer Kapazität und Verfahren zur dessen Herstellung

摘要

The present invention relates to a capacitive microsensor comprising a sandwich of three silicon wafers (1, 2, 3), a peripheral strip of each face of the central wafer being adhesively bonded to a corresponding strip of the face opposite of an external wafer by means of an insulating strip (5, 6), at least one of the external wafers constituting a first electrode (22, 23), the central wafer constituting a second electrode (21) and at least a part of this central wafer forming a capacitor with variable capacitance with at least one of the external wafers. At least one of the insulating strips consists of a sandwich of a first insulating layer (5-1, 6-1), of a conducting layer (5-2, 6-2) and of a second insulating layer (5-3, 6-3), the conducting layer being combined with connection means (25, 26).