Method of initialisation of a serial link between two integrated circuits having a parallel/serial port and device using such method

摘要

The method uses an input-output port between a parallel bus and a serial link. The port uses two clocks of different frequency, a first being of high frequency for the serial link called the transmission clock (CKT/CKR), and a second of lower frequency for the signals arriving from the parallel bus called the system clock (CKS). The method involves a first step of re-initialisation of the port with isolation of the reception clock; a second step of the re-initialisation of the transmission clock logic (CKT); and a third and final step of returning to zero the serial link between the two ports. Re-initialisation includes a stage in which the microprocessor associated with the port to be re-initialised transmits a series of neutral messages which allows a reception delay line to extract a reception clock signal (CKR) then transmit a calibration signal (CAL) indicating that the reception clock is calibrated.