SYNCHRONOUS CONTROLLER

摘要

A synchronous controller comprising a memory (101) in which blocked data are stored, a clock generating circuit (102) which generates an input-side clock (Cin) in accordance with the rate of data to be synchronized and a memory control circuit (103) which generates an output-side clock (Cout ) in accordance with the input-side clock (Cin) from the clock generating circuit (102). The block-data are stored in the memory (101) in accordance with the input-side clock (Cin) and the stored blocked data are outputted from the memory (101) in units of a block in accordance with the output-side clock (Cout) from the memory control circuit (103). The difference between the quantity of the data inputted to the memory (101) and the quantity of the data outputted from the memory (101) is detected by the memory control circuit (103) and the speed of the output-side clock (Cout) is changed by the memory control circuit (103) in accordance with the detected differential quantity so as to be synchronized with the input-side clock (Cin) from the clock generating circuit. <IMAGE>