| 摘要 |
A calculation unit speedily calculates a division or square root according to an iteration algorithm with a partial remainder expressed with the sum of a sum digit and carry digit. The calculation unit has a quotient selection logic circuit. The quotient selection logic circuit at least has an adder for adding higher three bits of the sum digit to higher three bits of the carry digit, an OR gate for providing the OR of the fourth bits of the sum and carry digits, and a quotient digit determination block for determining the next quotient digit according to the outputs of the adder and OR gate.
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