发明名称 |
Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device |
摘要 |
A computer system is disclosed which has a master, such as a processor, a memory, and I/O device, a first transfer path, which includes a bus, and a second transfer path, which includes a transfer interconnection. Transfers between the memory and the I/O device are effected via the first path while transfers between the processor and the I/O device are transferred via the second path. The disparate treatment between these two types of transfers reduces the likelihood that the transfer via the second path is delayed and thereby reduces the likelihood that the master is totally blocked from operation.
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申请公布号 |
US5799207(A) |
申请公布日期 |
1998.08.25 |
申请号 |
US19950413807 |
申请日期 |
1995.03.28 |
申请人 |
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE |
发明人 |
WANG, SHIH-CHIEH;CHANG, WEI-WEN;HSU, ZEN-DAR |
分类号 |
G06F13/40;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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