发明名称 PSEUDO FAULT GENERATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a pseudo fault generation circuit capable of falsely generating a fault with respect to line data on an optional position in block data and obtaining accurate error information. SOLUTION: Only when an output side valid flag 3 is set up, a line counter circuit 7 is counted up. A comparator circuit 8 compares the count value of the circuit 7 with the value of a line indication register 5. When a pseudo fault instruction from a pseudo fault indication bit 6 is inputted through an AND circuit 9, a fault generation circuit 10 edits line data outputted front an output side register 1 to convert the data into line data causing the generation of a fault. A fault detection circuit 11 checks line data outputted from an input side register 2 and outputs a fault generation signal. An error register 15 individually stores a fault generation signal inputted through an AND circuit 14 or an AND circuit 12.
申请公布号 JPH10228392(A) 申请公布日期 1998.08.25
申请号 JP19970029106 申请日期 1997.02.13
申请人 NEC ENG LTD 发明人 TAKAHASHI HIROKI
分类号 G06F11/22;G06F13/00 主分类号 G06F11/22
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