| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a method and device for designing the clock tree of a semiconductor integrated circuit, which can be increased in degree of integration by adjusting all element-to-element wiring in the integrated circuit to become the shortest. SOLUTION: A clock tree is constructed by making a pre-layout, so as to increase the degree of integration of a Manhattan length semiconductor integrated circuit and calculating and checking Manhattan lengths, which are the distances in straight lines between an input clock buffer and a plurality of terminal flip-flops, and then, inserting a plurality of clock drivers so as to suppress the delay time to each terminal flip-flop from the input clock buffer to a small value. Than the final layout is made by deciding the wiring, so that the wiring length to each terminal flip flop becomes the shortest. Therefore, the delay time for each terminal flip-flop from a clock input terminal can be made nearly equal to one another, and the degree of integration of the semiconductor integrated circuit can be enhanced.</p> |
