| 摘要 |
An output buffer stores a supply voltage on a capacitor when an input is a logic "0", and boosts a boot voltage at the capacitor's first terminal above the supply voltage by an NMOS threshold voltage when the input is a logic "1". A PMOS transistor receives the boot voltage at its source and outputs the boot voltage at its drain when the boot voltage exceeds its gate voltage by a PMOS threshold voltage. A first NMOS transistor couples its drain to ground when its gate voltage exceeds the NMOS threshold voltage. A second NMOS transistor's gate is coupled to the PMOS and first NMOS transistors' drains, and the second NMOS transistor outputs the supply voltage at its source when its gate voltage exceeds the supply voltage by the NMOS threshold voltage. When the input is a logic "1", a control circuit drops the PMOS and first NMOS transistor's gate voltages to ground, thereby applying the boot voltage at the second NMOS transistor's gate and causing the second NMOS transistor to output the supply voltage. When the input is a logic "0", the control circuit raises the PMOS transistor's gate voltage to the supply voltage. The control circuit also raises the first NMOS transistor's gate voltage above the NMOS threshold voltage, but does so only after the boot voltage exceeds the PMOS transistor's gate voltage by less than the PMOS threshold voltage. Thus, the capacitor cannot discharge to ground because the PMOS and first NMOS transistors are never on simultaneously.
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