| 摘要 |
The invention provides a parallel to serial data converter wherein the frequency of a basic clock pulse signal to be applied for driving can be reduced to one half with respect to a same data rate and consequently the operation speed required for a circuit in a preceding stage can be reduced, and a bad influence of noise such as, for example, jitters of serial data is eliminated. In the parallel to serial data converter, a clock pulse signal having a frequency f/2 Hz equal to one half the data rate of parallel data which is f bps is used as a basic clock pulse signal, and an inverted pulse signal is produced from the basic clock pulse signal. Then, a rising or falling edge of each pulse of the basic clock pulse signal and a rising or falling edge of each pulse of the inverted pulse signal are detected, and a byte clock pulse signal having a frequency equal to that of the parallel data is produced by logical ORing of such two edge detection outputs and is supplied to a multiplexer.
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