| 摘要 |
Zero detect of a sum of binary operands is disclosed. If the sum is zero, the bit-complement of the sum is a string of one's, and therefore incrementing the string of one's generates a carry-out bit of one. Likewise, if the sum is non-zero, the bit-complement of the sum will contain one or more zero's, and therefore incrementing the bit-complemented sum will not generate a carry-out bit of one. One embodiment includes providing a result representing a bit-complement of the sum, and then inspecting a carry-out bit generated by incrementing the result. Another embodiment includes bit-complementing first and second operands, generating a first carry-out bit from a sum of the bit-complemented first and second operands and a constant of one, generating a second carry-out bit from a sum of the bit-complemented first and second operands and a constant of two, and setting a zero detect flag to TRUE when an EXCLUSIVE-OR of the first carry-out bit and the second carry-out bit is a one. Advantageously, the first and second carry-out bits can be generated concurrently using carry chains to provide rapid zero detect. The invention is well-suited for providing zero detect of the sum A+B where A and B are n-bit binary operands, as well as zero detect of the sum A+B+C where A and B are n-bit binary operands and C is a carry-in bit.
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