发明名称 Memory device in which electrical power consumption of power circuit thereof is reduced during an idle state
摘要 A memory device connected to a host computer is disclosed wherein when a power consumption reducing function is performed, the power consumption can be further reduced. The memory device includes a memory medium, a data read/write circuit, a power circuit, an electric power processing IC, an interface circuit, and an MPU. The interface circuit is connected to the portion of the power circuit on the upstream side of the electric power processing IC. The circuits including the MPU are connected to the portion of the power circuit on the downstream side of the electric power processing IC. The interface circuit is provided with a sleep signal generating circuit which generates a sleep signal which is sent to the power processing IC to stop the power supply to the downstream side of the power processing IC when a specific instruction signal is supplied from the host computer. Thus, the power consumption of the memory device can be remarkably reduced. The supply of the sleep signal is stopped immediately after an optical disc or the like is inserted in the drive.
申请公布号 US5799199(A) 申请公布日期 1998.08.25
申请号 US19960688905 申请日期 1996.07.31
申请人 FUJITSU LIMITED 发明人 ITO, MASAHIRO;ISATO, NOBUHIKO
分类号 G06F3/06;G06F1/32;H02J1/00;(IPC1-7):G06F1/00;G06F1/18;G06F1/26 主分类号 G06F3/06
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