| 摘要 |
<p>An information processing apparatus includes a central processing unit; a first and a second memory; a single CPU bus to which said first memory and said second memory are connected for transferring a memory address and a writing/reading control signal which are output from said central processing unit; means for controlling writing/reading to said first memory and said second memory, for decoding said memory address and said writing/reading control signal to make both of said first memory and said second memory in a state enabling writing or make only one of said first memory and said second memory in a state enabling reading.The same information is written into the duplex memories at the same time and the information can be read out independently from respective memories. A single CPU bus is sufficient for multiple memories, and duplex writing and individual reading are performed in a small quantity of hardware.</p> |
