| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device where processes specific to forming memory cells are lessened as much as possible and which reduces a cell size and enhances resistance to soft errors. SOLUTION: A gate oxide film 306 and a capacitor insulating film 310 are formed through the same oxide film forming process, and a gate electrode 305 and a charge holding electrode 309 are formed through the same electrode forming process. A capacitor electrode connection local wiring 311 and a bit line connection local wiring 312 are formed through the same electrode forming process, active regions 303 adjacent to each other in the direction of word lines are arranged deviating from each other by the width of the gate electrode 305, an isolating oxide film 302 region between passing word lines is arranged adjacent to a capacitor forming diffusion layer 307 in an active region 303 in the direction of Z-Z', and a trench 304 can be disposed in the isolation oxide film 302 between the passing word lines in a direction vertical to the long side of the active region 303. A charge holding electrode 309 pattern is not present, and the trench 304 is arranged as close to gates electrodes 305 located on both the sides of the trench 304 as one/forth the minimum isolation distance of a gate electrode. |
