BURIED MEMORY LOGIC ELEMENT UTILIZING AUTOMATICALLY ALIGNED SILICIDE AND MANUFACTURING METHOD THEREOF

摘要

PROBLEM TO BE SOLVED: To reduce the junction leak current to improve the characteristics of an element, by forming a first drain doped with a first impurity on a semiconductor substrate at one side of a first gate electrode, and first source doped with a second impurity on a semiconductor substrate at the other end of the gate electrode. SOLUTION: On a gate insulation film 48 a nondoped Si is deposited and patterned to form a first through third gate patterns 50a-c at a cell array region and peripheral circuit region. The entire surface of a semiconductor substrate 100 having these patterns 50a-c is doped with an n-type impurity to form low- concn. sources/drains 52a-c at a cell array region A, NMOS region B and PMOS region C. This reduces the junction leak current at the cell array region to avoid deteriorating the refresh characteristic of an EDL element.