| 发明名称 |
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| 摘要 |
The microprocessor resides along with its protected real address space in a secure module surrounded by tamper resistant circuitry pad. Encryption programs and encryption keys are stored in the protected memory. A second real address space is also connected to the address and data bus of the microprocessor in order to provide program and data space for a user. Gating circuitry prevent the exposure of instructions and data form the privileged memory from appearing outside of the secure module. The gating circuits switch address spaces by recognizing a sequence of predetermined addresses. |
| 申请公布号 |
JP2788590(B2) |
申请公布日期 |
1998.08.20 |
| 申请号 |
JP19930186307 |
申请日期 |
1993.07.28 |
| 申请人 |
INTAANASHONARU BIJINESU MASHIINZU CORP |
发明人 |
DENISU JII ABURAHAMU;SUCHIIBUN JII ADEN |
| 分类号 |
G06F1/00;G06F9/06;G06F12/14;G06F21/24 |
主分类号 |
G06F1/00 |
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