| 摘要 |
A decoding circuit for two sequential addresses including a function gate which shares both P type input transistor devices (53 and 55) between input terminals (A0# and A0-A4) and uses predecoders to remove P type devices from a central portion of available die space, and N type transistor devices (57) by utilizing a pass gate device (56) to join output terminals (D0 and D1) for the two sequential addresses when an address is not selected.
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