| 摘要 |
A DMA data transfer system is provided with an interrupt request controller that has pass through logic, data limit logic, stale data logic and error detecting logic to monitor for predetermined conditions. A request for an interrupt sent to a central processor is generated by the interrupt request controller when an input interrupt request is applied to the interrupt request controller and one of the following conditions is met: 1) no previous DMA requests had occurred for a predetermined time interval; 2) a preset limit for the amount of data being transferred is reached; 3) no new requests for DMA transfer occur for preset time intervals; or 4) the status indicates an error in the data being transferred, or priority handling of the data is requested. By making sure one of the predetermined conditions is met before generating an interrupt request, the number of interrupt requests to the central processing unit is greatly reduced and the throughput of the system is increased.
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