Input buffer circuit with hysteresis for noise control

摘要

In an interface for an input signal with a small amplitude and a high bit rate, the output voltage of a receiver can become more indeterminate when the input signal voltage at the receiving end of a signal transmission line becomes equal to a reference voltage Vref. In the input buffer circuit of the CMOS current mirror type, a transistor Q2 is connected in parallel with another transistor Q1, where the conductivity types of both the transistors are the same and a reference voltage Vref is applied to the gate electrode of the transistor Q1. The transistor Q2 endows the input buffer circuit with a hysteresis characteristic, and the output power N1 of the input buffer circuit is supplied to the gate electrode of the transistor Q2.