| 摘要 |
A memory circuit wherein subthreshold leakage current may be reduced. The memory circuit includes a memory array composed of one or more storage cells that are each configured to store a memory value on a storage transistor. The storage cells further include a write transistor coupled to the storage transistor that is configured to allow data driven on a write bit line to be stored to the storage transistor. The write bit line is coupled to a write control unit, which includes a buffer and a offset voltage element. The buffer is configured to establish an output voltage on the write bit line in response to an input voltage. The offset voltage element is coupled to the buffer, and is configured to offset the output voltage on the write bit line by a predetermined amount. In one implementation of the write control unit, the buffer is formed by an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a diode-connected transistor coupled between the inverter and ground. The diode-connected transistor has the effect of holding the write bit line at a level equal to its threshold voltage when the n-channel transistor of the inverter is active. In another implementation, the buffer is also an inverter that includes a p-channel and an n-channel transistor. The offset voltage element is a pullup transistor that is active when the n-channel transitor of the inverter is active. The pullup transistor forms a voltage divider with the n-channel transistor, such that the voltage between the write bit line and ground is offset by an amount determined by the voltage drop across the pullup transistor. The offset voltage established by the write control unit biases the write transistor such that subthreshold leakage current may be reduced when the write transistor is off.
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