发明名称 Rahmensynchronisiervorrichtung fuer einen biorthogonalen Decoder
摘要 1,230,343. Digital transmission systems. POST OFFICE. 16 April, 1969 [16 April, 1968], No. 19479/69. Headings H4L and H4P. Word synchronization in a digital data receiver is attained by comparison of a sync. word, transmitted repeatedly prior to the data, with a number of locally generated words each a cyclic permutation of the sync. word. As described, the data consists of 8-bit words and is preceded by four 8-bit sync. words preceded by a bit-rate clock signal. The sync. word chosen displays a good auto-correlation characteristic. When the receiver attains bit synchronization (not described) a pulse at terminal 16 causes gates 24 to be enabled and a word identical to the sync. word (11100100) to be placed in shift register 12. Clock pulses step the register at bit rate and consequently each stage of the register outputs repeatedly an 8-bit word, each word being a cyclic variation of the sync. word (e.g. the word from stage 5 is 10011100). The register stages are connected to respective multipliers 40, forming part of a correlator and which are also fed with the received signal from terminal 14. The multipliers feed integrators 44 and that integrator which is fed by the multiplier connected to the stage of register 12 presenting a signal which is in phase with the received sync. words develops a steadily increasing positive output, all other integrator outputs varying between zero or negative values. At a time after the pulse at 16 determined by monostable 36, decoder 46 enables that one of eight units 52 (two shown) which corresponds to the integrator having a positive output. Thus if the output of stage 5 is in phase with the sync. words decoder 46 enables the fifth unit 52. This unit now outputs a pulse whenever register 12 contains a word identical to that generated by stage 5 (i.e. 10011100), these pulses being in word synchronism with the received words and appearing as a word-rate clock at terminal 58. On occurrence of the first pulse from the enabled unit 52 integrators 44 are reset, gates 28 are enabled, and gates 24 inhibited. The correlator may now be used to correlate the data words with preset messages at terminals 62 (not described).
申请公布号 DE1919345(A1) 申请公布日期 1969.10.23
申请号 DE19691919345 申请日期 1969.04.16
申请人 COMMUNICATIONS SATELLITE CORP. 发明人 G. SCHMIDT,WILLIAM
分类号 H04L7/04 主分类号 H04L7/04
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