| 摘要 |
A semiconductor integratedd circuit device adopting a master slice scheme, having a cell array in which basic cells are arrayed in a matrix shape and on which first power source wiring lines, second power source wiring lines and third power source wiring lines are respectively stacked in succession from a lowermost layer toward an uppermost layer, the first power source wiring lines and the third power source wiring lines being both extended in a column direction while the second power source wiring lines are extended in a row direction; wherein second contact holes for connecting the second power source wiring line and the third power source wiring line are arranged, when viewed in plan, around first contact holes for connecting the first power source wiring line and the second power source wiring line, in a region in which the first power source wiring line, the second power source wiring line and the third power source wiring line intersect. The second contact holes are not arranged in those regions around the first contact holes into which the first contact holes shift in the extending direction of the second power source wiring line. In addition, the first contact holes and the second contact holes are automatically formed by placing first contact hole cells and second contact hole cells in a design automation system, respectively. |
