发明名称 A NONVOLATILE MEMORY STRUCTURE
摘要 <p>A nonvolatile Flash EEPROM array (500) comprises a plurality of blocks which comprises a plurality of sectors of NOR-gate transistors (300). Each transistor (302) has a drain (304), a source (306), and a control gate (314). The drains (304) of each transistor in a column are electrically coupled, the control gate (314) of each transistor in a row are electrically coupled, and the source (306) of all the transistors in a sector are electrically coupled. A sector of the nonvolatile Flash EEPROM array comprises 8 rows and 512 columns of transistors and a block comprises 128 vertically stacked sectors.</p>
申请公布号 WO1998035344(A2) 申请公布日期 1998.08.13
申请号 US1998002740 申请日期 1998.02.11
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