| 摘要 |
An antifuse based PROM cell design allows large currents to be sinked during cell programming to ensure low programmed resistance of the cell while using minimum-geometry select devices. This is achieved by utilizing a pseudo SCR latchup effect during programming. The regions in the semiconductor substrate (28a) forming lower antifuse electrodes for the antifuses in the PROM cells are doped at low levels with phosphorus. An antifuse layer (32a) formed from an oxide, oxide-nitride, or oxide-nitride-oxide antifuse layer, is formed over the lower antifuse electrode, and an upper antifuse electrode is formed from polysilicon. A minimum-geometry N-Channel select transistor is formed in series with the antifuse to complete the PROM cell. The drain (26a) and source (22a) diffusions of the select transistor are arsenic doped and the drain diffusion is contiguous with the lower antifuse electrode. A bit line (18a) is contacted to the upper antifuse electrode (34x) and the select transistor gate is part of a polysilicon word line. The source diffusion of the select transistor is grounded.
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