| 摘要 |
In a reading circuit for a semiconductor memory, connection between a bit line pair 3 and input line of a differential amplifier 4 is controlled using an address transition detection signal LTD. For equalizing the bit line pair 3 in pulse form after transition, the bit line pair 3 is connected to the input terminal of the differential amplifier 4 for a little longer period than the equalizing period, and for clamping the bit line pair 3, the bit line pair 3 and the input terminal of the differential amplifier 4 are disconnected from each other, thus allowing a high-speed, stable reading operation with large-scale capacity. |
