| 摘要 |
The present invention relates to semiconductor memory devices with high bandwidth architecture. The semiconductor memory device includes arrays (22) comprising a plurality of reference blocks storing a plurality of memory cells, a plurality of word lines (WL) extending in a length direction of the chip, a plurality of complementary bit line pairs (BL, BL) extending in another length direction of the chip, a plurality of complementary data I/O line pairs (IO, IO) arranged on the upper portion of the arrays and extending in the said other direction and each being connected to each pair of bit lines, and a plurality of column selection lines (CSL) arranged in the said other length direction and adjacent to the data I/O line pairs, for controlling connection of each pair of bit lines and the data I/O lines. |
