SYNCHRONOUS CLOCK GENERATOR INCLUDING DELAY-LOCKED LOOP

摘要

A data and command latching circuit (60) includes a delay-locked loop (62) driven by a continuous reference clock signal (CCLKREF) that generates a delayed output clock signal having a delay controlled by the delay-locked loop. The latching circuit (60) also includes a variable delay circuit (64) external to the delay-locked loop (62) that is driven by a discontinuous reference clock signal (DCLKREF). Delay of the external delay circuit (64) is controlled by a control voltage output from the delay-locked loop, so that the delays of the external delay circuit are determined with reference to the continuous reference clock signal (CCLKREF). The delayed clock signals from the delay-locked loop activate control data latches (66) to latch control data (CD1-CDN) arriving at the latch circuit (60). The delayed signals from the variable delay circuit (64) activate data latches (68) to latch data (DA1-DAM) arriving at the latch circuit (60).