| 摘要 |
A tunable balanced RC filter circuit of the type in which the resistors are formed as MOS transistors with variable gate voltages for tuning the filter. The MOS transistor takes the form of a series arrangement of individual MOS transistors (T1-1, T1-2, ..., T1-N; T2-1, T2-2, ..., T2-N) each having the same d.c. bias on its gate. The gate of each of the individual MOS transistors in the series arrangement also receives a fraction of the a.c. component of the input signal on the input terminals (IT1, IT2) of the two-port network by means of a resistor ladder (R1-1, R1-2, ..., R1-N, R2-1, R2-2, ..., R2-N), which is connected to the input terminals (IT1, IT2) via buffers (B1, B2). The a.c. component of the input signal is thus divided among the individual transistors in the series arrangement. In this way it is possible to use MOS transistors with a small gate voltage swing at comparatively large input voltages. |
