发明名称 Optimized planarization process for SOG filled vias
摘要 A planarization process, featuring removal of spin on glass, used to fill narrow spaces between metal lines, has been developed. A dual dielectric, of underlying silicon oxide, and overlying silicon nitride, are initially used to passivate the metal lines, followed by the spin on glass fill. A RIE etchback of the spin on glass proceeds to a point in which the silicon nitride, on the metal line, is exposed. The exposed silicon nitride is then removed leaving a silicon oxide passivated metal line, and seamless insulator filled spaces. The ability of not exposing the passivating silicon oxide to RIE echback process, allows seamless fills to result.
申请公布号 US5792705(A) 申请公布日期 1998.08.11
申请号 US19970921882 申请日期 1997.09.02
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 WANG, CHIN-KUN;HUANG, YUAN-CHANG;HSU, IMAN
分类号 H01L21/3105;(IPC1-7):H01L21/476 主分类号 H01L21/3105
代理机构 代理人
主权项
地址