| 摘要 |
An integrated circuit provides for doubled data throughput by clocking data on both edges of an attached clock signal. The circuit includes an upper latch stack, responsive to the clock rising edge, and a lower latch stack responsive to the clock falling edge, each latch stack outputting a respective set and clear signal. An active overlap filter logically ORs the set and clear signals from the upper and lower latch stacks to a third set and clear signal which controls operation of an output latch. Data lines are connected to the upper and lower latch stacks, such that a first data signal is clocked to the circuit output during a clock rising edge transition and a second data signal is clocked to the output during a clock falling edge transition. Filter circuitry between the latch stacks and the output latch ensures that set and clear are not asserted simultaneously, thus providing for "glitch" free operation of the circuit.
|
