Apparatus and method for generating a phase detection signal that coordinates the phases of separate clock signals

摘要

A phase detection signal is generated with a phase detection logic pipeline and its associated tapped pipeline signal combinational logic circuit. The phase detection logic pipeline generates phase detection logic pipeline output signals from a first input clock signal and a second input clock signal. The first input clock signal is applied to a first flip-flop of a set of serially connected flip-flops to generate a pipeline signal. The pipeline signal is driven through the set of serially connected flip-flops by the second clock input signal. Logic pipeline output nodes connected between the serially connected flip-flops carry the phase detection logic pipeline output signals. The phase detection logic pipeline output signals are applied to the tapped pipeline signal combinational logic circuit, which logically combines the signals to generate the phase detection signal.