发明名称 |
Method of modular reduction and modular reduction circuit |
摘要 |
A method of modular reduction P mod Q based on a precomputation. Two quantities are precomputed and stored in a look-up table. Based on these stored precomputed quantities, two stages of partial modular reduction are performed. The result of the second stage of partial modular reduction is then adjusted according to the value of Q, to determine the modular reduction result. The modular reduction result may be provided to variable radix multiplication logic circuitry.
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申请公布号 |
US5793659(A) |
申请公布日期 |
1998.08.11 |
申请号 |
US19960730197 |
申请日期 |
1996.10.15 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
CHEN, HONG-YI;GAI, WEI-XIN |
分类号 |
G06F7/72;(IPC1-7):G06F7/72;H04K1/00 |
主分类号 |
G06F7/72 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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