| 摘要 |
In a computer system an apparatus interconnects a first bus, a second bus and a frame buffer, wherein the first bus and the second bus are of incompatible bus architecture types. For example the first bus may be a loosely coupled bus having split-bus transaction capability, such as the ARBus, and the second bus may be a tightly ordered bus, such as the PCI local bus. The apparatus includes bridge hardware for converting access requests from the first bus into suitable requests for the second bus. Data paths within the apparatus allow data to be routed from one bus to another. The apparatus further includes a frame buffer controller that is accessible from either of the first or second buses for performing read or write operations from/to the frame buffer. Data path logic allows data to be routed from any of the first bus, second bus and frame buffer to any other one of these three locations. In a preferred embodiment, the data paths are fabricated on a first integrated circuit, and all of control logic is fabricated on a second integrated circuit. The partitioning of hardware in this manner allows for an efficient interface to be provided between the two chips.
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