| 摘要 |
A memory device and method of packaging to increase the production yield of large scale digital memory chips. The architecture provides the ability to house a plurality of partially defective memory chips into a single casing to provide the same memory as a non-defective chip, thus eliminating the need to discarding a chip having minor defects. The chips are divided into data blocks that can be individually tested and disabled so that only that defective block is discarded not the entire chip, thus increasing production yield.
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